Retraction
Performance improvement of elliptic curve cryptography system using low power, high speed 16 × 16 Vedic multiplier based on reversible logic
Paper Information
Record ID:
37718
Author(s):
Journal:
Publication Date:
March 06, 2020
Retraction Date:
June 14, 2022
(3.4 years years ago)
Subject:
Broad Categories:
Computer Science
Computer Science
Specific Fields:
Computer Science
Computer Science
Institutions:
Country:
🇮🇳 IndiaArticle Type:
Publisher:
Springer - Nature Publishing Group
Open Access:
Yes
PubMed ID:
Not indexed in PubMed
Retraction PubMed ID:
Not indexed in PubMed
Retraction Details
Citations (14)
14
Total Citations5
Post-Retraction(35.7%)
9
Pre-Retraction0
Same DayPost-Retraction Citation Analysis
0
Within 30 days
2
Within 1 year
1
After 2+ years
778
Days since retraction (latest)
Systematic exploration of N-bit Vedic multipliers: A roadmap of technological approaches in pursuit of future trends
Hemanshi Chugh, Sonal Singh
Nano Communication Networks
Published: Jul 2024
1 citation
1 citation
778 days after retraction
Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications
C. M. Kalaiselvi, R. S. Sabeenian
Analog Integrated Circuits and Signal Processing
Published: Feb 2024
6 citations
6 citations
605 days after retraction
Design of Area-speed Efficient Anurupyena Vedic Multiplier for Deep Learning Applications
C. M. Kalaiselvi, R. S. Sabeenian
Research Square (Research Square)
Open Access
Published: Jul 2023
2 citations
2 citations
408 days after retraction
Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique
B. Srikanth, J. V. R. Ravindra, P. Ramakrishna et al. (4 authors)
Wireless Personal Communications
Open Access
Published: Apr 2023
2 citations
2 citations
318 days after retraction
Delay-Efficient Vedic Multiplier Design Using 4:3 Counter for Complex Multiplication
M. Venkata Subbaiah, G. Umamaheswara Reddy
Lecture notes in electrical engineering
Published: Jan 2023
201 days after retraction
Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique
B. Srik, JVR. Ravindra, P. Ramakrishna et al. (4 authors)
Research Square (Research Square)
Open Access
Published: Jun 2022
1 citation
1 citation
12 days before retraction
Multiple Stuck At Fault Diagnosis System For Digital Circuit On FPGA Using Vedic Multiplier and ANN
Mangesh Islampurkar, Kishanprasad Gunale, S. B. Somani et al. (4 authors)
International Journal of Circuits Systems and Signal Processing
Open Access
Published: May 2022
15 days before retraction
Veda-PUF: A PUF based on Vedic Principles for Robust Lightweight Security for IoT
Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos et al. (5 authors)
2021 IEEE International Symposium on Smart Electronic Systems (iSES)
Published: Dec 2021
4 citations
4 citations
195 days before retraction
Report on Cryptographic Hardware Design using Vedic Mathematics
Saurabh Singh, Sunita Soni
2021 International Conference on Technological Advancements and Innovations (ICTAI)
Published: Nov 2021
216 days before retraction
Comparison and extension of high performance adders for hybrid and error tolerant applications
R. Jothin, C. Vasanthanayaki, P. Sreelatha et al. (4 authors)
Journal of Ambient Intelligence and Humanized Computing
Published: Nov 2021
223 days before retraction
Speed, power and area efficient 2D FIR digital filter using vedic multiplier with predictor and reusable logic
V. Dyana Christilda, A. Milton
Analog Integrated Circuits and Signal Processing
Published: May 2021
27 citations
27 citations
408 days before retraction
Improving security against cache memory attacks for dual field multiplier design based on elliptic curve cryptography
R. Vijay Sai, Har Narayan Upadhyay
Journal of Ambient Intelligence and Humanized Computing
Published: Jan 2021
525 days before retraction
Multiplier for DSP Application in CPS System
Abhishek Kumar
Advances in systems analysis, software engineering, and high performance computing book series
Published: Nov 2020
1 citation
1 citation
588 days before retraction
A novel reversible ternary coded decimal adder/subtractor
Mohammad-Ali Asadi, Mohammad Mosleh, Majid Haghparast
Journal of Ambient Intelligence and Humanized Computing
Published: Sep 2020
11 citations
11 citations
651 days before retraction
Quick Stats
Total Citations:
14
Years Since Retraction:
3.4 years
Open Access:
Yes
Last Checked:
Jul 24, 2025